Mentor extends Questa with formal coverage checks
Mentor Graphics has added three branches to its Questa formal verification suite that automate and in some cases streamline the formal verification of coverage checks, common problems hard to detect in...
View ArticleReal Intent state machine debug focuses on core errors
Real Intent has updated its Ascent Implied Intent Verification (IIV) tool with analysis functions that pinpoint important errors in finite state machines to reduce the time it takes to sift through...
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On-chip interconnect startup uses network theory to sidestep deadlocks
A startup aims to cut SoC integration time using theories developed for much larger computer networks. NetSpeed Systems has developed in addition to a network-on-chip (NoC) architecture a set of tools...
View ArticleApplications won’t find all the bugs, but they have their uses
Applications or test cases extracted automatically from them should be very good for exercising hardware. The hardware has to run them anyway. They are large and complex, so should test many different...
View ArticleDebug monitors look for deadlock
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework, aiming to provide a way of picking up bus-contention problems without the need to stream out large amounts of...
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Wally Rhines looks beyond ‘endless verification’ to the system era
At the first DVCon China, Wally Rhines, chairman and CEO of Mentor – A Siemens business, offered a comprehensive overview of the challenges facing verification and how they are growing, nine years...
View ArticleToward more efficient formal strategies for deadlock
Deadlock is one of those problems that is well established but has remained a persistent challenge. Whether the issue manifests itself as a total or ‘true’ deadlock, or as one from which a device can...
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Second formal check aids deadlock hunting
Arm and Mentor proposed adding a second assertions check to a traditional deadlock-hunting process in a high profile paper at this year’s virtual Design Automation Conference. In the paper ‘Easy...
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